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28F016XS 16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY
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Backwards-Compatible with 28F008SA Command-Set 2 A Typical Deep Power-Down 1 mA Typical Active I CC Current in Static Mode 16 Separately-Erasable/Lockable 128-Kbyte Blocks 1 Million Erase Cycles per Block State-of-the-Art 0.6 m ETOXTM IV Flash Technology
Effective Zero Wait-State Performance up to 33 MHz Synchronous Pipelined Reads SmartVoltage Technology User-Selectable 3.3V or 5V V CC User-Selectable 5V or 12V V PP 0.33 MB/sec Write Transfer Rate Configurable x8 or x16 Operation 56-Lead TSOP and SSOP Type I Package
Intel's 28F016XS 16-Mbit flash memory is a revolutionary architecture which is the ideal choice for designing truly revolutionary high-performance products. Combining very high read performance with the intrinsic nonvolatility of flash memory, the 28F016XS eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory, such as DRAM, for improved system performance. The innovative capabilities of the 28F016XS enable the design of directexecute code and mass storage data/file flash memory systems. The 28F016XS is the highest performance high-density nonvolatile read/program flash memory solution available today. Its synchronous pipelined read interface, flexible VCC and VPP voltages, extended cycling, fast program and read performance, symmetrically-blocked architecture, and selective block locking provide a highly flexible memory component suitable for resident flash component arrays on the system board or SIMMs. The synchronous pipelined interface and x8/x16 architecture of the 28F016XS allow easy interface with minimal glue logic to a wide range of processors/buses, providing effective zero wait-state read performance up to 33 MHz. The 28F016XS's dual read voltage allows the same component to operate at either 3.3V or 5.0V VCC. Programming voltage at 5V VPP minimizes external circuitry in minimal-chip, space critical designs, while the 12.0V VPP option maximizes program/erase performance. Its high read performance combined with flexible block locking enable both storage and execution of operating systems/application software and fast access to large data tables. The 28F016XS is manufactured on Intel's 0.6 m ETOX IV process technology.
November 1996
Order Number: 290532-004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F016XS may contain design defects or errors known as errata. Current characterized errata are available upon request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683
COPYRIGHT (c) INTEL CORPORATION, 1996 CG-041493
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CONTENTS
PAGE 1.0 INTRODUCTION ............................................ 7 1.1 Product Overview ........................................ 7 2.0 DEVICE PINOUT........................................... 10 2.1 Lead Descriptions ...................................... 12 3.0 MEMORY MAPS ........................................... 14 3.1 Extended Status Register Memory Map..... 15 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS............. 16 4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH)........................................... 16 4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL) ........................................... 17 4.3 28F008SA--Compatible Mode Command Bus Definitions.......................................... 18 4.4 28F016XS--Enhanced Command Bus Definitions ................................................. 19 4.5 Compatible Status Register ....................... 20 4.6 Global Status Register ............................... 21 4.7 Block Status Register ................................ 22 4.8 Device Configuration Code ........................ 23 4.9 SFI Configuration Table ............................. 23
28F016XS FLASH MEMORY
PAGE 5.0 ELECTRICAL SPECIFICATIONS ................. 24 5.1 Absolute Maximum Ratings ....................... 24 5.2 Capacitance............................................... 24 5.3 Transient Input/Output Reference Waveforms............................................... 26 5.4 DC Characteristics (VCC = 3.3V) ................ 27 5.5 DC Characteristics (VCC = 5.0V) ................ 30 5.6 Timing Nomenclature ................................. 33 5.7 AC Characteristics--Read Only Operations ................................................ 34 5.8 AC Characteristics for WE#--Controlled Write Operations ....................................... 40 5.9 AC Characteristics for CE X#--Controlled Write Operations ....................................... 44 5.10 Power-Up and Reset Timings .................. 48 5.11 Erase and Program Performance............. 49 6.0 MECHANICAL SPECIFICATIONS ................ 51 APPENDIX A: Device Nomenclature and Ordering Information .................................. 53 APPENDIX B: Additional Information............... 54
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28F016XS FLASH MEMORY
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REVISION HISTORY
Description
Number -001 -002 Original Version
Removed support of the following features: * All page buffer operations (read, write, programming, Upload Device Information) * Command queuing * Software Sleep and Abort * Erase all Unlocked Blocks and Two-Byte Write * RY/BY# Configuration as part of the Device Configuration command Changed definition of "NC." Removed "No internal connection to die" from description. Added "xx" to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4. Modified parameters "V" and "I" of Section 5.1 to apply to "NC" pins. Increased IPPR (VPP Read Current) for VPP > VCC to 200 A at VCC = 3.3V/5.0V. Changed VCC = 5.0V DC Characteristics (Section 5.5) marked with Note 1 to indicate that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a TTL rise/fall time of <10 ns. Corrected tPHCH (RP# High to CLK) to be a "Min" specification at V CC = 3.3V/5.0V. Corrected the graphical representation of tWHCH and tEHCH in Figures 15 and 16. Increased Typical "Byte/Word Program Times" (tWHRH1A/tWHRH1B) for VPP = 5.0V (Sec. 5.13): tWHRH1A from 16.5 s to 29.0 s and t WHRH1B from 24.0 s to 35.0 s at V CC = 3.3V tWHRH1A from 11.0 s to 20.0 s and t WHRH1B from 16.0 s to 25.0 s at V CC = 5.0V. Increased Typical "Block Program Times" (tWHRH2/ tWHRH3) for VPP = 5.0V (Section 5.13): tWHRH2 from 2.2 sec to 3.8 sec and t WHRH3 from 1.6 sec to 2.4 sec at V CC = 3.3V tWHRH2 from 1.6 sec to 2.8 sec and t WHRH3 from 1.2 sec to 1.7 sec at V CC = 5.0V. Changed "Time from Erase Suspend Command to WSM Ready" spec name to "Erase Suspend Latency Time to Read;" Modified typical values and Added Min/Max values at VCC =3.3/5.0V and VPP =5.0/12.0V (Section 5.13). Minor cosmetic changes throughout document.
-003
Added 3/5# pin to Pinout Configuration (Figure 2), Product Overview (Section 1.1) and Lead Descriptions (Section 2.1) Modified Block Diagram (Figure 1): Removed Address Counter; Added 3/5# pin Added 3/5# pin to Test Conditions of ICCS Specifications Added 3/5# pin (Y) to Timing Nomenclature (Section 5.6) Removed Note 7 of Section 5.7 Modified Device Configuration Code: Incorporated RY/BY# Configuration (Level Mode support ONLY) Modified Power-Up and Reset Timings (Section 5.10) to include 3/5# pin: Removed t5VPH and t3VPH specifications; Added t PLYL, tPLYH, tYLPH, and tYHPH specifications Added SSOP pinout (Figure 2) and Mechanical Specifications Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0) Minor cosmetic changes throughout document.
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Number -004
28F016XS FLASH MEMORY
REVISION HISTORY (Continued) Description Require all VCC Tolerences to be within 5% of Operational Voltage IPPES Is Pushed to 200 A from 50 Max ICCD Is Pushed to 10 A from 5 Max Updated tAVAV at 3.3V Updated tELEH at 3.3V and 5.0V
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28F016XS FLASH MEMORY
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1.0 INTRODUCTION
The documentation of the Intel 28F016XS Flash memory device includes this datasheet, a detailed user's manual, a number of application notes and design tools, all of which are referenced in Appendix B. The datasheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User's Manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the Intel 28F008SA. Significant 28F016XS feature revisions occurred between datasheet revisions 290532-001 and 290532-002. These revisions center around removal of the following features: * * * * * All page buffer operations (read, write, programming, Upload Device Information) Command queuing Software Sleep and Abort Erase all Unlocked Blocks and Two-Byte Write RY/BY# Configuration options * * * *
28F016XS FLASH MEMORY
The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and result in greater product reliability and ease-of-use as compared to other flash memories. Significant features of the 28F016XS as compared to previous asynchronous flash memories include: Synchronous Pipelined Read Interface Significantly Improved Read and Program Performance SmartVoltage Technology Selectable 3.3V or 5.0 VCC Selectable 5.0V or 12.0 VPP Block Program/Erase Protection
In addition, a significant 28F016XS change occurred between datasheet revisions 290532-002 and 290532-003. This change centers around the addition of a 3/5# pin to the device's pinout configuration. Figures 2 and 3 show the 3/5# pin assignment for the TSOP and SSOP Type I packages. Intel recommends that all customers obtain the latest revisions of 28F016XS documentation.
The 28F016XS's synchronous pipelined interface dramatically raises read performance far beyond previously attainable levels. Addresses are synchronously latched and data is read from a 28F016XS bank every 30 ns (5V VCC, SFI Configuration = 2). This capability translates to zero wait-state reads at clock rates up to 33 MHz at 5V VCC, after an initial address pipeline fill delay and assuming even and odd banks within the flash memory are alternately accessed. Data is latched and driven valid 20 ns (tCHQV) after a rising CLK edge. The 28F016XS is capable of operating up to 50 MHz (5V VCC); its programmable SFI Configuration enables system design flexibility, optimizing the 28F016XS to a specific system clock frequency. See Section 4.9, SFI Configuration Table, for specific SFI Configurations for given operating frequencies. The SFI Configuration optimizes the 28F016XS for a wide range of system operating frequencies. The default SFI Configuration is 4, which allows system boot from the 28F016XS at any frequency up to 50 MHz at 5V VCC. After initiating an access, data is latched and begins driving on the data outputs after a CLK count corresponding to the SFI Configuration has elapsed. The 28F016XS will hold data valid until CE# or OE# is deactivated or a CLK count corresponding to the SFI Configuration for a subsequent access has elapsed. The CLK and ADV# inputs, new to the 28F016XS in comparison to previous flash memories, control address latching and device synchronization during read operations. The CLK input controls the device latencies, times out the SFI Configuration counter and synchronizes data outputs. ADV# indicates the presence of a valid address on the 28F016XS 7
1.1
Product Overview
The 28F016XS is a high-performance, 16-Mbit (16,777,216-bit) block erasable nonvolatile random access memory organized as either 1 Mword x 16 or 2 Mbyte x 8, subdivided into even and odd banks. Address A1 makes the bank selection. The 28F016XS includes sixteen 128-Kbyte (131,072 byte) blocks or sixteen 64-Kword (65,536 word) blocks. Chip memory maps for x8 and x16 modes are shown in Figures 4 and 5.
28F016XS FLASH MEMORY
address inputs. During read operations, addresses are latched and accesses are initiated on a rising CLK edge in conjunction with ADV# low. Both CLK and ADV# are ignored by the 28F016XS during command/data write sequences. The 28F016XS incorporates SmartVoltage technology, providing VCC operation at both 3.3V and 5.0V and program and erase capability at VPP = 12.0V or 5.0V. Operating at VCC = 3.3V, the 28F016XS consumes less than one half the power consumption at 5.0V VCC, while 5.0V VCC provides highest read performance capability. VPP operation at 5.0V eliminates the need for a separate 12.0V converter, while the VPP = 12.0V option maximizes program/erase performance. In addition to the flexible program and erase voltages, the dedicated VPP gives complete code protection with VPP VPPLK. A 3/5# input pin configures the device's internal circuitry for optimal 3.3V or 5.0V read/program operation. A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation. Internal Algorithm Automation allows program and block erase operations to be executed using a TwoWrite command sequence to the CUI in the same way as the 28F008SA 8-Mbit FlashFileTM memory. Software locking of memory blocks is an added feature of the 28F016XS as compared to the 28F008SA. The 28F016XS provides selectable block locking to protect code or data such as directexecutable operating systems or application code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the 28F016XS has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set. Writing of memory data is performed in either byte or word increments, typically within 6 s at 12.0V VPP, which is a 33% improvement over the 28F008SA. A block erase operation erases one of the 16 blocks in typically 1.2 sec, independent of the other blocks. Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve one million
Block Erase Cycles by providing wear-leveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems and hard disk drive designs. All operations are started by a sequence of Write commands to the device. Three Status Registers (described in detail later in this datasheet) and a RY/BY# output pin provide information on the progress of the requested operation. The following Status Registers are used to provide device and WSM operation information to the user: * A Compatible Status Register (CSR) which is 100% compatible with the 28F008SA FlashFile memory Status Register. The CSR, when used alone, provides a straightforward upgrade capability to the 28F016XS from a 28F008SAbased design. A Global Status Register (GSR) which also informs the system of overall Write State Machine (WSM) status. 16 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status.
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*
*
The GSR and BSR memory maps for Byte-Wide and Word-Wide modes are shown in Figures 5 and 6. The 28F016XS incorporates an open drain RY/BY# output pin. This feature allows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. The 28F016XS also incorporates a dual chipenable function with two input pins, CE0# and CE1#. These pins have exactly the same functionality as the regular chip-enable pin, CE#, on the 28F008SA. For minimum chip designs, CE1# may be tied to ground and system logic may use CE0# as the chip enable input. The 28F016XS uses the logical combination of these two signals to enable or disable the entire chip. Both CE0# and CE1# must be active low to enable the device. If either one becomes inactive, the chip will be disabled. This feature, along with the open drain RY/BY# pin, allows the system designer to reduce the number of control pins used in a large array of 16-Mbit devices.
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DQ 8-15 DQ 0-7 Output Buffer Output Buffer Input Buffer Data Register ID Register CLK ADV#
28F016XS FLASH MEMORY
Input Buffer
3/5#
I/O Logic
BYTE#
Output Multiplexer
CSR
CE0# ESRs OE#
CE1 #
0-20
CUI
A
Data Comparator Input Buffer
WE# WP# RP#
Even Address Latch
Y Decoder
Y Gating/Sensing
128-Kbyte
128-Kbyte
WSM
Address Register
128-Kbyte
128-Kbyte
X Decoder
Even Bank
RY/BY# VPP 3/5# VCC GND
Block 14
Odd Address Latch
X Decoder
Odd Bank
Y Decoder
Y Gating/Sensing
Block 15
Program/Erase Voltage Switch
Block 0
Block 1
0532_01
Figure 1. 28F016XS Block Diagram Architectural Evolution Includes Synchronous Pipelined Read Interface, SmartVoltage Technology, and Extended Status Registers
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28F016XS FLASH MEMORY
The BYTE# pin allows either x8 or x16 read/programs to the 28F016XS. BYTE# at logic low selects 8-bit mode with address A0 selecting between low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit operation with address A1 becoming the lowest order address and address A0 is not used (don't care). A device block diagram is shown in Figure 1. The 28F016XS incorporates an Automatic Power Saving (APS) feature, which substantially reduces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical ICC current is 1 mA at 5.0V (3 mA at 3.3V). A deep power-down mode of operation is invoked when the RP# (called PWD# on the 28F008SA) pin transitions low. This mode brings the device power consumption to less than 2.0 A, typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time of 300 ns (5V VCC) is required from RP# switching high before latching an address into the
28F016XS. In the deep power-down state, the WSM is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared. A CMOS standby mode of operation is enabled when either CE0# or CE1# transitions high and RP# stays high with all input control pins at CMOS levels. In this mode, the device typically draws an ICC standby current of 70 A at 5V V CC. The 28F016XS is available in 56-Lead, 1.2 mm thick, 14 mm x 20 mm TSOP and 1.8 mm thick, 16 mm x 23.7 mm SSOP Type I packages. The form factor and pinout of these two packages allow for very high board layout densities.
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2.0
DEVICE PINOUT
The 28F016XS is pinout compatible with the 28F016SA/SV 16-Mbit FlashFile memory components, providing a performance upgrade path to the 28F016XS. The 28F016XS 56-Lead TSOP and SSOP pinout configurations are shown in Figures 2 and 3.
28F016SA/SV 3/5# CE1 # NC A 20 A 19 A 18 A 17 A16 V CC A 15 A14 A 13 A 12 CE0 # V PP RP# A 11 A 10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
28F016SA/SV
3/5# CE 1 # NC A 20 A 19 A 18 A 17 A16 V CC A 15 A14 A 13 A 12 CE 0 # V PP RP# A 11 A 10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
E28F016XS 56-LEAD TSOP PINOUT
14 mm x 20 mm TOP VIEW
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
WP# WE# OE# RY/BY# DQ15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ 3 DQ 10 DQ 2 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# ADV# CLK
WP# WE# OE# RY/BY# DQ15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ 3 DQ 10 DQ 2 VCC DQ 9 DQ1 DQ8 DQ0 A0 BYTE# NC NC
0532_02
Figure 2. 28F016XS 56-Lead TSOP Pinout Configuration Shows Compatibility with the 28F016SA/SV, Allowing for Easy Performance Upgrades from Existing 16-Mbit Designs
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28F016SA/SV CE0 # A 12 A 13 A 14
A 15 3/5# CE1 # NC A 20 A 19 A 18 A 17 A 16 VCC GND DQ 6 DQ 14 DQ 7 DQ 15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC CE0 # A12 A13 A 14 A 15 3/5# CE1 # NC A 20 A 19 A 18 A 17 A 16 VCC GND DQ 6 DQ 14 DQ 7 DQ 15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC 1 2 3 4
28F016XS FLASH MEMORY
28F016SA/SV 56 55 54 53 52 51 50 49 48 47 46 DA28F016XS 56-LEAD SSOP STANDARD PINOUT 16 mm x 23.7 mm TOP VIEW 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VPP RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ 9 DQ 1 DQ 8 DQ 0 A0 BYTE# ADV# CLK
DQ2 DQ 10
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VPP RP# A11 A10 A9 A1 A2
A3 A4 A5 A6 A7
GND A8 VCC DQ 9 DQ 1 DQ 8 DQ 0
A0
BYTE# NC NC
DQ2
DQ 3 DQ 11 GND
DQ 10 DQ 3 DQ 11 GND
XS_SSOP
Figure 3. 28F016XS 56-Lead SSOP Pinout Configuration Shows Compatibility with the 28F016SA/SV, Allowing for Easy Performance Upgrades from Existing 16-Mbit Designs
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28F016XS FLASH MEMORY
2.1
Lead Descriptions
Type INPUT Name and Function
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Symbol A0
BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8 mode. This address is latched in x8 data programs and ignored in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). BANK-SELECT ADDRESS: Selects an even or odd bank in a selected block. A 128-Kbyte block is subdivided into an even and odd bank. A 1 = 0 selects the even bank and A1 = 1 selects the odd bank, in both byte-wide mode and wordwide mode device configurations. WORD-SELECT ADDRESSES: Select a word within one 128-Kbyte block. Address A1 and A7-16 select 1 of 2048 rows, and A2-6 select 16 of 512 columns. These addresses are latched during both data reads and programs. BLOCK-SELECT ADDRESSES: Select 1 of 16 erase blocks. These addresses are latched during data programs, erase and lock-block operations. LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles. Outputs array, identifier or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. HIGH-BYTE DATA BUS: Inputs data during x16 data program operations. Outputs array or identifier data in the appropriate read mode; not used for Status Register reads. Outputs floated when the chip is de-selected, the outputs are disabled (OE# = VIH) or BYTE# is driven active. CHIP ENABLE INPUTS: Activate the device's control logic, input buffers, decoders and sense amplifiers. With either CE0# or CE1# high, the device is de-selected and power consumption reduces to standby levels upon completion of any current data program or erase operations. Both CE0# and CE1# must be low to select the device. All timing specifications are the same for both signals. Device Selection occurs with the latter falling edge of CE0# or CE1#. The first rising edge of CE0# or CE1# disables the device.
A1
INPUT
A2-A16
INPUT
A17-A20 DQ0-DQ7
INPUT INPUT/ OUTPUT INPUT/ OUTPUT
DQ8-DQ15
CE0#, CE1#
INPUT
RP#
INPUT
RESET/POWER-DOWN: RP# low places the device in a deep power-down state. All circuits that consume static power, even those circuits enabled in standby mode, are turned off. When returning from deep power-down, a recovery time of t PHCH is required to allow these circuits to power-up. When RP# goes low, the current WSM operation is terminated, and the device is reset. All Status Registers return to ready, clearing all status flags. Exit from deep power-down places the device in read array mode. OUTPUT ENABLE: Drives device data through the output buffers when low. The outputs float to tri-state off when OE# is high. CE x# overrides OE#, and OE# overrides WE#. WRITE ENABLE: Controls access to the CUI, Data Register and Address Latch. WE# is active low, and latches both address and data (command or array) on its rising edge.
OE#
INPUT
WE#
INPUT
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2.1
Symbol CLK ADV# RY/BY#
28F016XS FLASH MEMORY
Lead Descriptions (Continued)
Type INPUT Name and Function CLOCK: Provides the fundamental timing and internal operating frequency. CLK latches input addresses in conjunction with ADV#, times out the desired output SFI Configuration as a function of the CLK period, and synchronizes device outputs. CLK can be slowed or stopped with no loss of data or synchronization. CLK is ignored during program operations. ADDRESS VALID: Indicates that a valid address is present on the address inputs. ADV# low at the rising edge of CLK latches the address on the address inputs into the flash memory and initiates a read access to the even or odd bank depending on the state of A1. ADV# is ignored during program operations. READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY/BY# high indicates that the WSM is ready for new operations, erase is suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE# or CE0#, CE1# are high). WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit for each block. When WP# is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent data programs or erases. When WP# is high, all blocks can be written or erased regardless of the state of the lock-bits. The WP# input buffer is disabled when RP# transitions low (deep power-down mode). BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or output on DQ0-7, and DQ8-15 float. Address A 0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A 0 input buffer. Address A1 then becomes the lowest order address. 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V operation. 3/5# low configures internal circuits for 5.0V operation. NOTE: Reading the array with 3/5# high in a 5.0V system could damage the device. Reference the power-up and reset timings (Section 5.10) for 3/5# switching delay to valid data. PROGRAM/ERASE POWER SUPPLY (12.0V 0.6V, 5.0V 0.5V) : For erasing memory array blocks or writing words/bytes into the flash array. VPP = 5.0V 0.5V eliminates the need for a 12.0V converter, while the 12.0V 0.6V option maximizes program/erase performance. Successful completion of program and erase attempts is inhibited with V PP at or below 1.5V. Program and erase attempts with VPP between 1.5V and 4.5V, between 5.5V and 11.4V, and above 12.6V produce spurious results and should not be attempted.
INPUT
OPEN DRAIN OUTPUT
WP#
INPUT
BYTE#
INPUT
3/5#
INPUT
VPP
SUPPLY
VCC
SUPPLY
DEVICE POWER SUPPLY (3.3V 5%, 5.0V 5%): To switch 3.3V to 5.0V (or vice versa), first ramp V CC down to GND, and then power to the new VCC voltage. Do not leave any power pins floating.
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28F016XS FLASH MEMORY
2.1
Lead Descriptions (Continued)
Type SUPPLY Name and Function GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NO CONNECT: Lead may be driven or left floating.
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x16 Mode 64-Kword Block 15 64-Kword Block 14 64-Kword Block 13 64-Kword Block 12 64-Kword Block 11 64-Kword Block 10 64-Kword Block 9 64-Kword Block 8 64-Kword Block 7 64-Kword Block 6 64-Kword Block 5 64-Kword Block 4 64-Kword Block 3 64-Kword Block 2 64-Kword Block 1 64-Kword Block 0
0532_03
Symbol GND NC
3.0
MEMORY MAPS
x8 Mode 128-Kbyte Block 15 128-Kbyte Block 14 128-Kbyte Block 13 128-Kbyte Block 12 128-Kbyte Block 11 128-Kbyte Block 10 128-Kbyte Block 9 128-Kbyte Block 8 128-Kbyte Block 7 128-Kbyte Block 6 128-Kbyte Block 5 128-Kbyte Block 4 128-Kbyte Block 3 128-Kbyte Block 2 128-Kbyte Block 1 128-Kbyte Block 0
1C0000 1BFFFF 1A0000 19FFFF 180000 17FFFF 160000 15FFFF 140000 13FFFF 120000 11FFFF 100000 0FFFFF 0E0000 0DFFFF 0C0000 0BFFFF 0A0000 09FFFF 080000 07FFFF 060000 05FFFF 040000 03FFFF 020000 01FFFF 000000
A 20-0
1FFFFF 1E0000 1DFFFF
A 20-1
FFFFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000
0532_04
Figure 4. 28F016XS Memory Map (Byte-Wide Mode)
Figure 5. 28F016XS Memory Map (Word-Wide Mode)
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3.1
x8 Mode
28F016XS FLASH MEMORY
Extended Status Register Memory Map
A 20-0 1FFFFFH
x16 Mode
A 20-1 FFFFFH
RESERVED
RESERVED
RESERVED GSR RESERVED BSR 15 RESERVED RESERVED
1E0006H 1E0005H 1E0004H 1E0003H
F0003H RESERVED GSR RESERVED BSR 15 F0002H
1E0002H 1E0001H 1E0000H
F0001H RESERVED RESERVED
. . .
RESERVED
. . .
RESERVED
F0000H
01FFFFH
0FFFFH
000006H RESERVED 000005H GSR 000004H RESERVED BSR 0 RESERVED RESERVED 000003H BSR 0 000002H RESERVED 000001H 000000H
0532_05
00003H RESERVED GSR 00002H RESERVED
00001H
RESERVED
00000H
0532_06
Figure 6. Extended Status Register Memory Map (Byte-Wide Mode)
Figure 7. Extended Status Register Memory Map (Word-Wide Mode)
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28F016XS FLASH MEMORY
4.0 4.1
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS Bus Operations for Word-Wide Mode (BYTE# = VIH)
Mode Notes 1,9,10 1,9 RP# VIH VIH CE0-1# VIL VIL OE# X X WE# VIH VIH ADV# VIL VIH CLK A1 X X DQ0-15 X X
E
RY/BY# X X X X X VOH VOH VOH X
Latch Read Address Inhibit Latching Read Address Read Output Disable Standby Deep Power-Down Manufacturer ID Device ID Write
1,2,7,9 1,6,7,9 1,6,7,9 1,3 1,4,9 1,4,8,9 1,5,6,9
VIH VIH VIH VIL VIH VIH VIH
VIL VIL VIL X VIL VIL VIL
VIL VIH X X VIL VIL VIH
VIH VIH X X VIH VIH VIL
X X X X X X X
X X X X
X X X X VIL VIH X
DOUT High Z High Z High Z 0089H 66A8H DIN
NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for data pins depending on whether or not OE# is active. 2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended, or the device is in deep power-down mode, RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation is in progress. 3. RP# at GND 0.2V ensures the lowest deep power-down current. 4. A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero. 5. Commands for erase, data program, or lock-block operations can only be completed successfully when V = VPPH1 or PP VPP = VPPH2. 6. While the WSM is running, RY/BY# stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a write operation). 8. The 28F016XS shares an identical device identifier with the 28F016XD. 9. CE0-1# at VIL is defined as both CE0# and CE1# low, and CE0-1# at VIH is defined as either CE0# or CE1# high. 10. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address A1 = 0 selects the even bank and A1 = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.
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4.2
Mode Latch Read Address Read Output Disable Standby Deep Power-Down Manufacturer ID Device ID Write
28F016XS FLASH MEMORY
Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Notes 1,9,10 1,9 RP# VIH VIH CE0-1# VIL VIL OE# X X WE# VIH VIH ADV# VIL VIH CLK A0 X X DQ0-7 X X RY/BY# X X
Inhibit Latching Read Address
1,2,7,9 1,6,7,9 1,6,7,9 1,3 1,4,9 1,4,8,9 1,5,6,9
VIH VIH VIH VIL VIH VIH VIH
VIL VIL VIH X VIL VIL VIL
VIL VIH X X VIL VIL VIH
VIH VIH X X VIH VIH VIL
X X X X X X X
X X X X
X X X X VIL VIH X
DOUT High Z High Z High Z 89H A8H DIN
X X X VOH VOH VOH X
NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for data pins depending on whether or not OE# is active. 2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended, or the device is in deep power-down mode, RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation is in progress. 3. RP# at GND 0.2V ensures the lowest deep power-down current. 4. A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero. 5. Commands for erase, data program, or lock-block operations can only be completed successfully when V = VPPH1 or PP VPP = VPPH2. 6. While the WSM is running, RY/BY# stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a program operation). 8. The 28F016XS shares an identical device identifier with the 28F016XD. 9. CE0-1# at VIL is defined as both CE0# and CE1# low, and CE0-1# at VIH is defined as either CE0# or CE1# high. 10. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address A1 = 0 selects the even bank and A1 = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.
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28F016XS FLASH MEMORY
4.3
28F008SA--Compatible Mode Command Bus Definitions
First Bus Cycle Command Notes Oper Write 1 2 3 Write Write Write Write Write Write Write Addr X X X X X X X X Data
(4)
E
Addr AA IA X Data(4) AD ID CSRD PA PA BA X PD PD xxD0H xxD0H
Second Bus Cycle Oper Read Read Read
Read Array Intelligent Identifier Read Compatible Status Register Clear Status Register Program Alternate Program Block Erase/Confirm Erase Suspend/Resume
xxFFH xx90H xx70H xx50H xx40H xx10H xx20H xxB0H
Write Write Write Write
ADDRESS AA = Array Address BA = Block Address IA = Identifier Address PA = Program Address X = Don't Care
DATA AD = Array Data CSRD = CSR Data ID = Identifier Data PD = Program Data
NOTES: 1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes. 2. The CSR is automatically available after device enters data program, erase, or suspend operations. 3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register definitions. 4. The upper byte of the data bus (D8-15) during command writes is a "Don't Care" in x16 operation of the device.
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4.4
ADDRESS
28F016XS FLASH MEMORY
28F016XS--Enhanced Command Bus Definitions
First Bus Cycle Command Notes 1 Oper Write Write 2 3
DATA AD = Array Data BSRD = BSR Data GSRD = GSR Data DCCD = Device Configuration Code Data
Second Bus Cycle
(4)
Addr X X X X
Data
Oper Read Write Write Write
Addr RA BA X X
Data(4) GSRD BSRD xxD0H xxD0H DCCD
Read Extended Status Register Lock Block/Confirm Upload Status Bits/Confirm Device Configuration
xx71H xx77H xx97H xx96H
Write Write
BA = Block Address RA = Extended Register Address PA = Program Address X = Don't Care
NOTES: 1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register memory maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. 3. This command sets the SFI Configuration allowing the device to be optimized for the specific sytem operating frequency. 4. The upper byte of the Data bus (D8-15) during command writes is a "Don't Care" in x16 operation of the device.
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28F016XS FLASH MEMORY
4.5
Compatible Status Register
WSMS 7 ESS 6 ES 5 DWS 4 VPPS 3 R 2 NOTES: R 1
E
R 0 RY/BY# output or WSMS bit must be checked to determine completion of an operation (erase, erase suspend, or data program) before the appropriate Status bit (ESS, ES or DWS) is checked for success. If DWS and ES are set to "1" during an erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again.
CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy
CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase In Progress/Completed CSR.5 = ERASE STATUS 1 = Error In Block Erasure 0 = Successful Block Erase CSR.4 = DATA WRITE STATUS 1 = Error in Data Program 0 = Data Program Successful CSR.3 = VPP STATUS 1 = VPP Error Detect, Operation Abort 0 = VPP OK The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP's level only after the Data Program or Erase command sequences have been entered, and informs the system if V PP has not been switched on. VPPS is not guaranteed to report accurate feedback between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min), and above VPPH2(max).
CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the CSR.
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4.6
WSMS 7
28F016XS FLASH MEMORY
Global Status Register
OSS 6 DOS 5 R 4 R 3 R 2 NOTES: R 1 R 0
GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy
RY/BY# output or WSMS bit must be checked to determine completion of an operation (block lock, suspend, Upload Status Bits, erase or data program) before the appropriate Status bit (OSS or DOS) is checked for success.
GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running GSR.4-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the GSR.
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28F016XS FLASH MEMORY
4.7
BS 7
Block Status Register
BLS 6 BOS 5 R 4 R 3 VPPS 2 NOTES: VPPL 1
E
R 0 RY/BY# output or BS bit must be checked to determine completion of an operation (block lock, suspend, erase or data program) before the appropriate Status bits (BOS, BLS) is checked for success.
BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy
BSR.6 = BLOCK LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running BSR.2 = VPP STATUS 1 = VPP Error Detect, Operation Abort 0 = VPP OK BSR.1 = VPP LEVEL 1 = VPP Detected at 5.0V 10% 0 = VPP Detected at 12.0V 5% BSR.1 is not guaranteed to report accurate feedback between the VPPH1 and VPPH2 voltage ranges. Programs and erases with VPP between VPPLK(max) and VPPH1 (min), between VPPH1(max) and VPPH2(min), and above VPPH2(max) produce spurious results and should not be attempted.
BSR.4,3,0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the BSRs.
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4.8
R 7
28F016XS FLASH MEMORY
Device Configuration Code
R 6 SFI2 5 SFI1 4 SFI0 3 R 2 NOTES: R 1 RB 0
DCC.5-DCC.3 = SFI CONFIGURATION (SFI2-SFI0) 001 = SFI Configuration 1 010 = SFI Configuration 2 011 = SFI Configuration 3 100 = SFI Configuration 4 (Default) DCC.0 = RY/BY# CONFIGURATION (RB) 1 = Level Mode (Default)
Default SFI Configuration on power-up or return from deep power-down mode is 4, allowing system boot from the 28F016XS at any frequency up to the device's maximum frequency. Undocumented combinations of SFI2-SFI0 are reserved by Intel Corporation for future implementations and should not be used. Undocumented combinations of RB are reserved by Intel Corporation for future implementations and should not be used.
DCC.7-DCC.6, DCC.2-DCC.1 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use. Set these bits to "0" when modifying the Device Configuration Code.
4.9
SFI Configuration Table
Notes 1 28F016XS-15 Frequency (MHz) 50 (and below) 50 (and below) 33 (and below) 16.7 (and below) 28F016XS-20 Frequency (MHz) 50 (and below) 37.5 (and below) 25 (and below) 12.5 (and below) 28F016XS-25 Frequency (MHz) 40 (and below) 30 (and below) 20 (and below) 10 (and below)
SFI Configuration 4 3 2 1
NOTE: 1. Default SFI Configuration after power-up or return from deep power-down mode via RP# low.
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28F016XS FLASH MEMORY
5.0 5.1
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings*
E
NOTICE: This is a production datasheet. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Temperature Under Bias ....................0C to +80C Storage Temperature ................... -65C to +125C
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
VCC = 3.3V 5% Systems Symbol TA VCC VPP V I IOUT Parameter Operating Temperature, Commercial VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on any Pin (except VCC,VPP) with Respect to GND Current into any Non-Supply Pin Output Short Circuit Current Notes 1 2 2,3 2,5 5 4 Min 0 -0.2 -0.2 -0.5 Max 70 7.0 14.0 VCC + 0.5 30 100 Units C V V V mA mA Test Conditions Ambient Temperature
VCC = 5.0V 5% Systems Symbol TA VCC VPP V I IOUT Parameter Operating Temperature, Commercial VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on any Pin (except VCC,VPP) with Respect to GND Current into any Non-Supply Pin Output Short Circuit Current Notes 1 2 2,3 2,5 5 4 Min 0 -0.2 -0.2 -2.0 Max 70 7.0 14.0 7.0 30 100 Units C V V V mA mA Test Conditions Ambient Temperature
NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20 ns. Maximum DC voltage on input/output pins is VCC +0.5V which may overshoot to VCC +2.0V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output sho rted at a time. 5. This specification also applies to pins marked "NC."
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5.2
Symbol CIN COUT CLOAD Symbol CIN COUT CLOAD
28F016XS FLASH MEMORY
Capacitance
Parameter Capacitance Looking into an Address/Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Notes 1 1 1, 2 Typ 6 8 Max 8 12 50 Units pF pF pF Test Conditions TA = +25C, f = 1.0 MHz TA = +25C, f = 1.0 MHz For the 28F016XS-20 and 28F016XS-25
For a 3.3V 5% System:
For 5.0V 5% System: Parameter Capacitance Looking into an Address/Control Pin Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Notes 1 1 1, 2 Typ 6 8 Max 8 12 100 30 Units pF pF pF pF Test Conditions TA = +25C, f = 1.0 MHz TA = +25C, f = 1.0 MHz For the 28F016XS-20 For the 28F016XS-15
NOTE: 1. Sampled, not 100% tested. Guaranteed by design. 2. To obtain iBIS models for the 28F016XS, please contact your local Intel/Distribution Sales Office.
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28F016XS FLASH MEMORY
5.3
Transient Input/Output Reference Waveforms
E
2.0 OUTPUT 0.8
0532_07
2.4 INPUT 0.45
2.0 TEST POINTS 0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 8. Transient Input/Output Reference Waveform (VCC = 5.0V 5%) for Standard Testing Configuration(1)
3.0 INPUT 0.0
0532_08
1.5
TEST POINTS
1.5
OUTPUT
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns.
Figure 9. Transient Input/Output Reference Waveform (VCC = 3.3V 5%) High Speed Reference Waveform(2) (VCC = 5.0V 5%)
NOTES: 1. Testing characteristics for 28F016XS-20 at 5V VCC. 2. Testing characteristics for 28F016XS-15 at 5V VCC and 28F016XS-20/28F016XS-25 at 3.3V VCC.
26
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5.4
Symbol ILI ILO ICCS
28F016XS FLASH MEMORY
DC Characteristics
VCC = 3.3V 5%, T A = 0C to +70C 3/5# = Pin Set High for 3.3V Operations Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 1,5 70 Min Typ Max 1 10 130 Units A A A Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND VCC = VCC Max CE0#, CE1#, RP# = VCC 0.2V BYTE#, WP#, 3/5# = V CC 0.2V or GND 0.2V VCC = VCC Max CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = V IH or VIL RP# = GND 0.2V BYTE# = VCC 0.2V or GND 0.2V VCC = VCC Max CMOS: CE0# ,CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V 4-Location Access Sequence: 3-1-1-1 (clocks) f = 25 MHz, I OUT = 0 mA VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V 4-Location Access Sequence: 3-1-1-1 (clocks) f = 16 MHz, I OUT = 0 mA
1
4
mA
ICCD
VCC Deep Power-Down Current VCC Word/Byte Read Current
1
2
5
A
ICCR1
1,4,5
65
85
mA
ICCR2
VCC Word/Byte Read Current
1,4, 5,6
60
75
mA
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28F016XS FLASH MEMORY
5.4
DC Characteristics (Continued)
E
Typ 8 8 Max 12 17 12 17 6 10 200 5 15 25 10 20 200 0.8 VCC +0.3 0.4 Units mA mA mA mA mA A A A mA mA mA mA A V V V V V VCC = VCC Min IOL = 4 mA VCC = VCC Min IOH = -2.0 mA VCC = VCC Min IOH = -100 A Test Conditions VPP = 12.0V 5% Program in Progress VPP = 5.0V 10% Program in Progress VPP = 12.0V 5% Block Erase in Progress 9 VPP = 5.0V 10% Block Erase in Progress CE0#, CE1# = VIH Block Erase Suspended VPP VCC VPP > VCC RP# = GND 0.2V VPP = 12.0V 5% Program in Progress Program in Progress VPP = 12.0V 5% Block Erase in Progress VPP = 5.0V 10% Block Erase in Progress VPP = VPPH1 or VPPH2 Block Erase Suspended 6 3 1 30 0.2 10 15 4 14
VCC = 3.3V 5%, T A = 0C to +70C 3/5# = Pin Set High for 3.3V Operations Symbol ICCW Parameter VCC Program Current Notes 1,6 Min
ICCE
VCC Block Erase Current
1,6
ICCES IPPS IPPR IPPD IPPW
VCC Erase Suspend Current VPP Standby/Read Current VPP Deep PowerDown Current VPP Program Current VPP Erase Current
1,2 1 1 1,6
IPPE
1,6
IPPES VIL VIH VOL VOH1 VOH2
VPP Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
1 6 6 6 6 2.4 VCC -0.2 -0.3 2.0
30
28
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5.4
Symbol VPPLK VPPH1 VPPH2 VLKO
28F016XS FLASH MEMORY
DC Characteristics (Continued)
VCC = 3.3V 5%, T A = 0C to +70C 3/5# = Pin Set High for 3.3V Operations Parameter VPP Erase/Program Lock Voltage VPP during Program/Erase Operations VPP during Program/Erase Operations VCC Erase/Program Lock Voltage Notes 3,6 Min 0.0 Typ Max 1.5 Units V Test Conditions
3
4.5
5.0
5.5
V
3
11.4
12.0
12.6
V
2.0
V
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V or 5.0V, T = +25C. These currents are valid for all product versions (package and speeds). 2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases, programs and lock block operations are inhibited when VPP VPPLK and not guaranteed in the ranges between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max). 4. Automatic Power Savings (APS) reduces ICCR to 3 mA typical in static operation. 5. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 6. Sampled, but not 100% tested. Guaranteed by design.
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5.5
DC Characteristics
E
Notes 1 1 1,5 70 Min Typ Max 1 10 130 Units A A A Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND VCC = VCC Max CE0#, CE1#, RP# = VCC 0.2V BYTE#, WP#, 3/5# = V CC 0.2V or GND 0.2V VCC = VCC Max CE0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = VIH or VIL RP# = GND 0.2V BYTE# = VCC 0.2V or GND 0.2V VCC = VCC Max CMOS: CE0# ,CE1# = GND 0.2V, BYTE# = GND 0.2V or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V 4-Location Access Sequence: 3-1-1-1 (clocks) f = 33 MHz, I OUT = 0 mA VCC = VCC Max CMOS: CE0#, CE1# = GND 0.2V, BYTE# = GND 0.2V, or VCC 0.2V, Inputs = GND 0.2V or VCC 0.2V 4-Location Access Sequence: 3-1-1-1 (clocks) f = 20 MHz, I OUT = 0 mA 2 4 mA
VCC = 5.0V 5%, T A = 0C to +70C 3/5# = Pin Set Low for 5.0V Operations Symbol ILI ILO ICCS Parameter Input Load Current Output Leakage Current VCC Standby Current
ICCD
VCC Deep PowerDown Current VCC Read Current
1
2
5
A
ICCR1
1,4,5
120
175
mA
ICCR2
VCC Read Current
1,4, 5,6
105
150
mA
30
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5.5
Symbol ICCW ICCE ICCES IPPS IPPR IPPD IPPW
28F016XS FLASH MEMORY
DC Characteristics (Continued)
VCC = 5.0V 5%, T A = 0C to +70C 3/5# = Pin Set Low for 5.0V Operations Parameter VCC Program Current Notes 1,6 Min Typ 25 25 VCC Erase Suspend Current 1,6 18 20 VCC Block Erase Current VPP Standby/Read Current VPP Deep PowerDown Current VPP Program Current 1 1,6 1,2 1 5 1 30 0.2 7 17 IPPE VPP Block Erase Current 1,6 5 16 IPPES VIL VIH VOL VOH1 VOH2 VPP Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 1 6 6 6 6 0.85 VCC VCC -0.4 -0.5 2.0 30 Max 35 40 25 30 10 10 200 5 12 22 10 20 200 0.8 VCC +0.5 0.45 Units mA mA mA mA mA A A A mA mA mA mA A V V V V VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A Test Conditions VPP = 12.0V 5% Program in Progress VPP = 5.0V 10% Program in Progress VPP = 12.0V 5% Block Erase in Progress VPP = 5.0V 10% Block Erase in Progress CE0#, CE1# = VIH Block Erase Suspended VPP VCC VPP > VCC RP# = GND 0.2V VPP = 12.0V 5% Program in Progress VPP = 5.0V 10% Program in Progress VPP = 12.0V 5% Block Erase in Progress VPP = 5.0V 10% Block Erase in Progress VPP = VPPH1 or VPPH2 Block Erase Suspended
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5.5
DC Characteristics (Continued)
E
Typ Max 1.5 Units V Test Conditions 5.0 5.5 V 12.0 12.6 V V
VCC = 5.0V 5%, TA = 0C to +70C 3/5# = Pin Set Low for 5.0V Operations Symbol VPPLK Parameter VPP Program/Erase Lock Voltage VPP during Program/Erase Operations VPP during Program/Erase Operations VCC Program/Erase Lock Voltage Notes 3,6 Min 0.0
VPPH1
4.5
VPPH2
11.4
VLKO
2.0
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V or 5.0V, T = +25C. These currents are valid for all product versions (package and speeds) and are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a TTL rise/fall time of <10 ns. 2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases, programs and lock block operations are inhibited when VPP VPPLK and not guaranteed in the ranges between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max). 4. Automatic Power Saving (APS) reduces ICCR to 1 mA typical in static operation. 5. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 6. Sampled, but not 100% tested. Guaranteed by design.
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5.6
A C D Q E F G W P R V Y 5V 3V
28F016XS FLASH MEMORY
Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V. For 5.0V systems, use the standard JEDEC cross point definitions (standard testing) or from where signals cross 1.5V (high speed testing). Each timing parameter consists of five characters. Some common examples are defined below: tELCH time(t) from CE# (E) going low (L) to CLK (C) going high (H) tAVCH time(t) from address (A) valid (V) to CLK (C) going high (H) tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X) Pin Characters Address Inputs CLK (Clock) Data Inputs Data Outputs CE# (Chip Enable) BYTE# (Byte Enable) OE# (Output Enable) WE# (Write Enable) RP# (Deep Power-Down Pin) RY/BY# (Ready Busy) ADV# (Address Valid) 3/5# Pin VCC at 4.5V Minimum VCC at 3.0V Minimum H L V X Z L High Low Valid Driven, but Not Necessarily Valid High Impedance Latched Pin States
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28F016XS FLASH MEMORY
5.7
AC Characteristics--Read Only Operations(1)
Versions(3) 28F016XS-20 Notes Min Max 50 20 6 6 4 4 6 25 20 20 0 0 20 30 480 2 2,6 2,6 2 2 6 0 0 30 0 6 0 30 0 480 6 0 35 25 25 0 0 25 25 8.5 8.5
E
28F016XS-25 Min Max 40 Units MHz ns ns ns 4 4 ns ns ns ns ns ns ns ns 35 ns ns ns ns 30 ns ns 30 ns ns
VCC = 3.3V 5%, T A = 0C to +70C
Symbol fCLK tCLK tCH tCL tCLCH tCHCL tELCH tVLCH tAVCH tCHAX tCHVH tGLCH tCHQV tPHCH tCHQX tELQX tEHQZ tGLQX tGHQZ tOH
Parameter CLK Frequency CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time CEX# Setup to CLK ADV# Setup to CLK Address Valid to CLK Address Hold from CLK ADV# Hold from CLK OE# Setup to CLK CLK to Data Delay RP# High to CLK Output Hold from CLK CEX# to Output Low Z CEX# High to Output High Z OE# to Output Low Z OE# High to Output High Z Output Hold from CEX# or OE# Change, Whichever Occurs First
34
E
5.7
Symbol fCLK tCLK tCH tCL tCLCH tCHCL tELCH tVLCH tAVCH tCHAX tCHVH tGLCH tCHQV tPHCH tCHQX tELQX tEHQZ tGLQX tGHQZ tOH
28F016XS FLASH MEMORY
AC Characteristics--Read Only Operations(1) (Continued)
Versions(3) Parameter CLK Frequency CLK Period CLK High Time CLK Low Time CLK Rise Time CLK Fall Time CEX# Setup to CLK ADV# Setup to CLK Address Valid to CLK Address Hold from CLK ADV# Hold from CLK OE# Setup to CLK CLK to Data Delay RP# High to CLK Output Hold from CLK CEX# to Output Low Z CEX# High to Output High Z OE# to Output Low Z OE# High to Output High Z Output Hold from CEX# or OE# Change, Whichever Occurs First 2 2,6 2,6 2 2 6 0 0 30 0 300 5 0 30 0 30 6 25 15 15 0 0 15 20 300 5 0 30 15 3.5 3.5 4 4 30 20 20 0 0 20 30 Notes 28F016XS-15(4) Min Max 66 20 6 6 4 4 28F016XS-20(5) Min Max 50 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VCC = 5.0V 5%, T A = 0C to +70C
NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements. 2. Sampled, not 100% tested. Guaranteed by design. 3. Device speeds are defined as: 15 ns at VCC = 5.0V equivalent to 20 ns at VCC = 3.3V 20 ns at VCC = 5.0V equivalent to 25 ns at VCC = 3.3V 4. See the high speed AC Input/Output Reference Waveforms. 5. See the standard AC Input/Output Reference Waveforms. 6. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
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28F016XS FLASH MEMORY
E
t
CH
t CL
t
CLCH
t CHCL t CLK
0532_09
Figure 10. CLK Waveform
CLK
ADDR t CHAX
A1
t AVCH ADV#
1 CLK Periods
t VLCH CEx# t CHVH
t EHQZ
t GHQZ t ELCH t ELQX
OE# t GLCH t GLQX DATA Even Odd Even Odd
t OH
t CHQX
t CHQV
0532_10
NOTE: 1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank accesses; the length of the burst access is dictated by the control CPU or bus architecture.
Figure 11. Read Timing Waveform(1) (SFI Configuration = 1, Alternate-Bank Accesses) 36
E
CLK ADDR t CHAX A1 2 CLK Periods t AVCH ADV#
28F016XS FLASH MEMORY
t VLCH CEx# t CHVH
t EHQZ
t GHQZ t ELCH t ELQX
OE# t GLCH t GLQX Even DATA Odd Even Odd
t OH
t CHQX
t CHQV
0532_11
NOTE: 1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank accesses; the length of the burst access is dictated by the control CPU or bus architecture.
Figure 12. Read Timing Waveform(1) (SFI Configuration = 2, Alternate-Bank Accesses)
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28F016XS FLASH MEMORY
E
t EHQZ
CLK
ADDR
tCHAX A1 3 CLK Periods tAVCH ADV#
tVLCH CEx# t CHVH
tGHQZ tELCH OE# tGLCH Even tGLQX DATA Odd
Note 2
tELQX
tOH Even Odd
Note 2
tCHQX
tCHQV
0532_12
NOTES: 1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank accesses; the length of the burst access is dictated by the control CPU or bus architecture. 2. Depending on the actual operation frequency, a consecutive alternating bank access can be initiated one clock period earlier. See AP-398 Designing with the 28F016XS for further information.
Figure 13. Read Timing Waveform(1) (SFI Configuration = 3, Alternate-Bank Accesses)
38
E
CLK ADDR tCHAX A1 4 CLK Periods tAVCH ADV#
28F016XS FLASH MEMORY
tVLCH tCHVH CEx#
tEHQZ
tGHQZ tELCH OE# tGLCH Even tGLQX DATA Odd Even Odd tELQX
tOH
tPHCH
tCHQX
tCHQV
RP#
0532_13
NOTE: 1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank accesses; the length of the burst access is dictated by the control CPU or bus architecture.
Figure 14. Read Timing Waveform(1) (SFI Configuration = 4, Alternating Bank Accesses)
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28F016XS FLASH MEMORY
5.8
AC Characteristics for WE#--Controlled Write Operations(1)
Versions 28F016XS-20 Notes Min 75 3 3,7 3,7 2,6 2,6 100 480 0 60 60 60 2 2 3,7 5 5 5 15 3 3 3 0 0 100 0 Typ Max
E
Max Unit ns ns ns ns ns ns ns ns ns ns ns ns 100 ns ns
VCC = 3.3V 5%, T A = 0C to +70C 28F016XS-25 Min 75 100 480 0 60 60 60 5 5 5 15 0 Typ
Symbol tAVAV tVPWH1,2 tPHEL tELWL tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHRL tRHPL
Parameter Write Cycle Time VPP Setup to WE# Going High RP# Setup to CEX# Going Low CEX# Setup to WE# Going Low Address Setup to WE# Going High Data Setup to WE# Going High WE# Pulse Width Data Hold from WE# High Address Hold from WE# High CEX# hold from WE# High WE# Pulse Width High Read Recovery before Write WE# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) data and RY/BY# High RP# High Recovery to WE# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High Duration of Program Operation Duration of Block Erase Operation
tPHWL tWHCH tQVVL1,2
3
480 20
480 20 0
ns ns s
3
0
tWHQV1 tWHQV2
3,4, 5,8 3,4
5 0.6
9 1.6
TBD 20
5 0.6
9 1.6
TBD 20
s sec
40
E
5.8
Symbol tAVAV tVPWH1,2 tPHEL tELWL tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHRL tRHPL
28F016XS FLASH MEMORY
AC Characteristics for WE#--Controlled Write Operations(1) (Continued)
Versions Parameter Write Cycle Time VPP Setup to WE# Going High RP# Setup to CEX# Going Low CEX# Setup to WE# Going Low Address Setup to WE# Going High Data Setup to WE# Going High WE# Pulse Width Data Hold from WE# High Address Hold from WE# High CEX# hold from WE# High WE# Pulse Width High Read Recovery before Write WE# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) data and RY/BY# High RP# High Recovery to WE# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High Duration of Program Operation Duration of Block Erase Operation 3 3 3 3 0 2 2 3,7 3 3,7 3,7 2,6 2,6 Notes 28F016XS-15 Min 65 100 300 0 50 50 50 0 5 5 15 0 100 0 Typ Max 28F016XS-20 Min 65 100 300 0 50 50 50 0 5 5 15 0 100 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VCC = 5.0V 5%, T A = 0C to +70C
tPHWL tWHCH tQVVL1,2
3
300 20 0
300 20 0
ns ns s
tWHQV1 tWHQV2
3,4, 5,8 3,4
4.5 0.6
6 1.2
TBD 20
4.5 0.6
6 1.2
TBD 20
s sec
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28F016XS FLASH MEMORY
NOTES: 1. Read timings during program and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. Guaranteed by design. 4. Program/erase durations are measured to valid Status Register (CSR) Data. 5. Program operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of WE# for all command program operations. 7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 8. Please contact Intel's Application Hotline or your local sales office for current TBD information.
E
42
E
CLK NOTE 6 DEEP POWER-DOWN
IH ADDRESSES (A) V IL NOTE 1
28F016XS FLASH MEMORY
WRITE DATA-WRITE OR ERASE SETUP COMMAND
WRITE VALID ADDRESS & DATA (DATA-WRITE) OR ERASE CONFIRM COMMAND A
AUTOMATED DATA-WRITE OR ERASE DELAY
WRITE READ EXTENDED REGISTER COMMAND
READ EXTENDED STATUS REGISTER DATA
V
IN t WHAX NOTE 3
A=RA
t
AVAV
t
V IH ADDRESSES (A) V IL NOTE 2 t AVAV t
AVWH A
READ COMPATIBLE STATUS REGISTER DATA
IN t WHAX
AVWH
ADV# NOTE 6
V CEx # (E) NOTE 4 V
IH
IL
t ELWL t WHEH
t
WHCH
V OE# (G) V
IH IL
t
WHWL
t
WHQV1,2
t
GHWL
V WE# (W) V
IH
IL
t t
WLWH t DVWH D
WHDX
V DATA (D/Q) V
IH
IL
HIGH Z t PHWL
IN
D
IN
D
IN
D
OUT
D
IN
t V RY/BY# (R) V OH OL
WHRL
t
V
RP# (P)
RHPL NOTE 5
IH IL
V
t V
V V
VPWH2
t
QVVL2
PPH2 PPH1 t PPLK
IL
V
PP
(V)
VPWH1
NOTE 7
t
QVVL1
V
NOTE 8
0532_14
NOTES: 1. This address string depicts data program/erase cycles with corresponding verification via ESRD. 2. This address string depicts data program/erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during data program/erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 5. RP# low transition is only to show tRHPL; not valid for above read and program cycles. 6. Data program/erase cycles are asynchronous; CLK and ADV# are ignored. 7. VPP voltage during data program/erase operations valid at both 12.0V and 5.0V. 8. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 15. AC Waveforms for WE#--Command Write Operations, Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read 43
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28F016XS FLASH MEMORY
5.9
AC Characteristics for CEX#--Controlled Write Operations(1)
Versions 28F016XS-20 Notes Min 80 3,7 3 3,7 2,6,7 2,6,7 7 2,7 2,7 3,7 7 3 3,7 3 0 100 480 0 60 60 65 10 10 5 15 0 100 0 Typ Max
E
Max Unit ns ns ns ns ns ns ns ns ns ns ns ns 100 ns ns
VCC = 3.3V 5%, T A = 0C to +70C 28F016XS-25 Min 75 100 480 0 60 60 60 10 10 5 15 0 Typ
Symbol tAVAV tVPEH1,2 tPHWL tWLEL tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL tRHPL
Parameter Write Cycle Time VPP Setup to CEX# Going High RP# Setup to WE# Going Low WE# Setup to CEX# Going Low Address Setup to CEX# Going High Data Setup to CEX# Going High CEX# Pulse Width Data Hold from CEX# High Address Hold from CEX# High WE hold from CEX# High CEX# Pulse Width High Read Recovery before Write CEX# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High RP# High Recovery to CEX# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High Duration of Program Operation Duration of Block Erase Operation
tPHEL tEHCH tQVVL1,2
3,7
480 20
480 20 0
ns ns s
3
0
tEHQV1 tEHQV2
3,4,5,8 3,4
5 0.6
9 1.6
TBD 20
5 0.6
9 1.6
TBD 20
s sec
44
E
5.9
Symbol tAVAV tVPEH1,2 tPHWL tWLEL tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL tRHPL
28F016XS FLASH MEMORY
AC Characteristics for CEX#--Controlled Write Operations(1) (Continued)
Versions Parameter Write Cycle Time VPP Setup to CEX# Going High RP# Setup to WE# Going Low WE# Setup to CEX# Going Low Address Setup to CEX# Going High Data Setup to CEX# Going High CEX# Pulse Width Data Hold from CEX# High Address Hold from CEX# High WE hold from CEX# High CEX# Pulse Width High Read Recovery before Write CEX# High to RY/BY# Going Low RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High RP# High Recovery to CEX# Going Low Write Recovery before Read VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High Duration of Program Operation Duration of Block Erase Operation 3 3,7 3 3,7 2,6,7 2,6,7 7 2,7 2,7 3,7 7 3 3,7 3 0 Notes 28F016XS-15 Min 60 100 300 0 45 45 50 0 5 5 15 0 100 0 Typ Max 28F016XS-20 Min 60 100 300 0 45 45 50 0 5 5 15 0 100 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VCC = 5.0V 5%, T A = 0C to +70C
tPHEL tEHCH tQVVL1,2
3,7
300 20 0
300 20 0
ns ns s
tEHQV1 tEHQV2
3,4,5,8 3,4
4.5 0.6
6 1.2
TBD 20
4.5 0.6
6 1.2
TBD 20
s sec
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28F016XS FLASH MEMORY
NOTES: 1. Read timings during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. Guaranteed by design. 4. Program/erase durations are measured to valid Status Register (CSR) Data. 5. Program operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of WE# for all command write operations. 7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 8. Please contact Intel's Application Hotline or your local sales office for current TBD information.
E
46
E
CLK NOTE 6 DEEP POWER-DOWN IH ADDRESSES (A) V IL NOTE 1 t AVAV t IH ADDRESSES (A) V NOTE 2 IL t AVAV t V AVEH NOTE 3 A IN t EHAX V WRITE DATA-WRITE OR ERASE SETUP COMMAND WRITE VALID ADDRESS & DATA (DATA-WRITE) OR ERASE CONFIRM COMMAND A AUTOMATED DATA-WRITE OR ERASE DELAY WRITE READ EXTENDED REGISTER COMMAND IN t EHAX AVEH ADV# NOTE 6 V WE# (W) V IL t
WLEL
28F016XS FLASH MEMORY
READ EXTENDED STATUS REGISTER DATA
A=RA
READ COMPATIBLE STATUS REGISTER DATA
IH
t
EHWH t EHCH
V OE# (G) V
IH IL
t V CEx#(E) V NOTE 4 IH IL t t V DATA (D/Q) V IL IH
ELEH DVEH
EHEL
t
EHQV1,2
t
GHEL
t
EHDX D D D D
HIGH Z
D
t
IN
IN
IN
OUT
IN
PHEL
t V RY/BY# (R) V OH OL
EHRL
t
RHPL NOTE 5
V RP# (P) V
IH IL
t V
V
VPEH2
t
QVVL2
PPH1 PPH2 t
PPLK
V (V) PP
V V
VPEH1
NOTE 7
t
QVVL1
IL NOTE 8
0532_15
NOTES: 1. This address string depicts data program/erase cycles with corresponding verification via ESRD. 2. This address string depicts data program/erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during data program/erase operations. 4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high. 5. RP# low transition is only to show tRHPL; not valid for above read and program cycles. 6. Data program/erase cycles are asynchronous; CLK and ADV# are ignored. 7. VPP voltage during data program/erase operations valid at both 12.0V and 5.0V. 8. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 16. AC Waveforms for CEX#--Controlled Write Operations, Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read 47
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28F016XS FLASH MEMORY
5.10
Power-Up and Reset Timings
E
t YLPH
5.0V
VCC POWER-UP
RP# (P)
t YHPH
3/5#
(Y)
t PLYL
3.3V
4.5V
VCC
0V
(3V,5V)
t PL5V
0532_18
NOTE: For read timings following reset see Section 5.7.
Figure 17. VCC Power-Up and RP# Reset Waveforms
Symbol tPLYL tPLYH tYLPH tYHPH tPL5V tPL3V
Parameter RP# Low to 3/5# Low (High) 3/5# Low (High) to RP# High RP# Low to VCC at 4.5V (Minimum) RP# Low to VCC at 3V (Min) or 3.6V (Max)
Notes
Min 0 0
Max
Unit s s s
2
0
NOTES: 1. The tYLPH and/or tYHPH times must be strictly followed to guarantee all other read and program specifications for the 28F016XS. 2. The power supply may start to switch concurrently with RP# going low.
48
E
5.11
Symbol tWHRH1A tWHRH1B tWHRH2 tWHRH3
28F016XS FLASH MEMORY
Erase and Program Performance(3,4)
Parameter Byte Program Time Word Program Time Block Program Time Block Program Time Block Erase Time Erase Suspend Latency Time to Read Notes 2,5 2,5 2,5 2,5 2,5 Min TBD TBD TBD TBD TBD 1.0 Typ(1) 29 35 3.8 2.4 2.8 12 Max TBD TBD TBD TBD TBD 75 Units s s sec sec sec s Byte Program Mode Word Program Mode Test Conditions
VCC = 3.3V 5%, V PP = 5.0V 5%, TA = 0C to +70C
VCC = 3.3V 5%, V PP = 12.0V 0.6V, T A = 0C to +70C Symbol tWHRH1 tWHRH2 tWHRH3 Parameter Program Time Block Program Time Block Program Time Block Erase Time Erase Suspend Latency Time to Read Notes 2,5 2,5 2,5 2 Min 5 TBD TBD 0.6 1.0 Typ(1) 9 1.2 0.6 1.6 9 Max TBD 4.2 2.0 20 55 Units s sec sec sec s Byte Program Mode Word Program Mode Test Conditions
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28F016XS FLASH MEMORY
5.11
Symbol tWHRH1A tWHRH1B tWHRH2 tWHRH3
Erase and Program Performance(3,4) (Continued)
Parameter Byte Program Time Word Program Time Block Program Time Block Program Time Block Erase Time Erase Suspend Latency Time to Read Notes 2,5 2,5 2,5 2,5 2,5 Min TBD TBD TBD TBD TBD 1.0 Typ(1) 20 25 2.8 1.7 2.0 9 Max TBD TBD TBD TBD TBD 55 Units s s sec sec sec s
E
Test Conditions Byte Program Mode Word Program Mode
VCC = 5.0V 5%, VPP = 5.0V 5%, TA = 0C to +70C
VCC = 5.0V 5%, VPP = 12.0V 0.6V, T A = 0C to +70C Symbol tWHRH1 tWHRH2 tWHRH3 Parameter Program Time Block Program Time Block Program Time Block Erase Time Erase Suspend Latency Time to Read Notes 2,5 2,5 2,5 2 Min 4.5 TBD TBD 0.6 1.0 Typ(1) 6 0.8 0.4 1.2 7 Max TBD 4.2 2.0 20 40 Units s sec sec sec s Byte Program Mode Word Program Mode Test Conditions
NOTES: 1. +25C, and nominal voltages. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, but not 100% tested. Guaranteed by design. 5. Please contact Intel's Application Hotline or your local sales office for current TBD information.
50
E
6.0
28F016XS FLASH MEMORY
MECHANICAL SPECIFICATIONS
048928.eps
Figure 18. Mechanical Specifications of the 28F016XS 56-Lead TSOP Type I Package Family: Thin Small Out-Line Package Symbol Minimum A A1 A2 b c D1 E e D L N Y Z 0.150 0.250 0 19.80 0.500 0.050 0.965 0.100 0.115 18.20 13.80 0.995 0.150 0.125 18.40 14.00 0.50 20.00 0.600 56 3 5 0.100 0.350 20.20 0.700 1.025 0.200 0.135 18.60 14.20 Millimeters Nominal Maximum 1.20 Notes
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28F016XS FLASH MEMORY
E
a E He A2 b R2 L1 Detail A R1 A Y C A1 See Detail A
0528_20
D
B
e 1
Figure 19. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package Family: Shrink Small Out-Line Package Symbol Minimum A A1 A2 B C D E e1 He N L1 Y a b R1 R2 2 3 0.15 0.15 3 4 0.20 0.20 0.45 15.70 0.47 1.18 0.25 0.13 23.40 13.10 Millimeters Nominal 1.80 0.52 1.28 0.30 0.15 23.70 13.30 0.80 16.00 56 0.50 0.55 0.10 4 5 0.25 0.25 16.30 Maximum 1.90 0.57 1.38 0.40 0.20 24.00 13.50 Notes
52
E
28F016XS FLASH MEMORY
APPENDIX A DEVICE NOMENCLATURE AND ORDERING INFORMATION
Product line designator for all Intel Flash products
DA2 8 F 0 1 6 XS - 1 5
Package DA = SSOP E = TSOP
Device Density 016 = 16 Mbit Product Family X = Fast Flash
Period of Maximum CLK Input Frequency (ns)
Device Type S = Synchronous Pipelined Interface
0532_20
Valid Combinations Option Order Code VCC = 3.3V 5%, 50 pF load, 1.5V I/O Levels(1) 28F016XS-20 28F016XS-25 28F016XS-20 28F016XS-25 28F016XS-20 28F016XS-20 28F016XS-15 VCC = 5.0V 5%, 100 pF load TTL I/O Levels(1) VCC = 5.0V 5%, 30 pF load 1.5V I/O Levels(1) 28F016XS-15
1 2 3 4
E28F016XS15 E28F016XS20 DA28F016XS15 DA28F016XS20
NOTE: 1. See Section 5.3 for Transient Input/Output Reference Waveforms.
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28F016XS FLASH MEMORY
APPENDIX B ADDITIONAL INFORMATION(1,2)
E
Order Number 297372 292147 292146 292163 292165 297500 297504 294016 297508 Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office Contact Intel/Distribution Sales Office
Document/Tool
16-Mbit Flash Product Family User's Manual AP-398 Designing with the 28F016XS AP-600 Performance Benefits and Power/Energy Savings of 28F016XSBased System Designs AP-610 Flash Memory In-System Code and Data Update Techniques AB-62 Compiled Code Optimizations for Flash Memories Interfacing the 28F016XS to the i960(R) Microprocessor Family Interfacing the 28F016XS to the Intel486TM Microprocessor Family ER-33 ETOXTM Flash Memory Technology--Insight to Intel's Fourth Generation Process Innovation
FLASHBuilder Utility 28F016XS Benchmark Utility Flash Cycling Utility 28F016XS iBIS Model 28F016XS VHDL Model 28F016XS TimingDesigner* Library Files 28F016XS Orcad/Viewlogic Schematic Symbols
NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and tools.
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